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19-1639; Rev 0; 1/00
Octal SMBus-to-Parallel I/O Expanders
General Description
The MAX1608/MAX1609 provide remote input/output (I/O) expansion through an SMBusTM 2-wire serial interface. Each device has eight high-voltage open-drain outputs that double as TTL-level logic inputs, providing continuous bidirectional capabilities. The open-drain outputs tailor the MAX1608/MAX1609 for use in load-switching and other level-shifting applications as well as general-purpose I/O applications. Two complete sets of registers allow the device and its outputs to be toggled between two states using the SMBSUS input, without the inherent latency of reprogramming outputs over the serial bus. The eight I/O lines are continuously monitored and can be used as inputs. Each line can generate asynchronous maskable interrupts on the falling edge, the rising edge, or both edges. For load-switching applications, the MAX1608 is designed to drive N-channel MOSFETs, and its outputs are low upon power-up; the MAX1609 is designed to drive Pchannel MOSFETs, and its I/Os are high impedance upon power-up. Other features of both devices include thermaloverload and output-overcurrent protection, ultra-low supply current, and a wide +2.7V to +5.5V supply range. The MAX1608/MAX1609 are available in space-saving 16-pin QSOP packages. o 8 General-Purpose Digital I/O Pins (withstand +28V) o SMBus 2-Wire Serial Interface o Supports SMBSUS Asynchronous Suspend o 9 Pin-Selectable Slave Addresses o Outputs High Impedance on Power-Up (MAX1609) o Outputs Low on Power-Up (MAX1608) o 2.5A Supply Current o +2.7V to +5.5V Supply Range o 16-Pin QSOP Package
Features
o Serial-to-Parallel or Parallel-to-Serial Conversions
MAX1608/MAX1609
Ordering Information
PART MAX1608EEE MAX1609EEE TEMP. RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 16 QSOP
Applications
Parallel I/O Expansion Power-Plane Switching Notebook and Desktop Computers Servers and Workstations Notebook Docking Stations Industrial Equipment
+2.7V TO +5.5V
Typical Operating Circuits
Pin Configuration
V+
100k 0.1F
100k
100k
TOP VIEW
IO0 1 IO1 2 IO2 3 IO3 4 IO4 5 IO5 6 IO6 7 IO7 8 16 V+ 15 SMBSUS 14 SMBCLK
MAX1609
ALERT SMBUS TO/ FROM HOST SMBDATA SMBCLK SMBSUS IO1 IO2 IO3
P-CH
MAX1608 MAX1609
13 ALERT 12 SMBDATA
ADD1
11 ADD1 10 ADD0 9 GND
LOAD1 GND IO7
LOAD2
LOAD3
ADD
QSOP SMBus is a trademark of Intel Corp.
Typical Operating Circuits continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
ABSOLUTE MAXIMUM RATINGS
V+ to GND ................................................................-0.3V to +6V IO_ to GND .............................................................-0.3V to +30V IO_ Sink Current..................................................-1mA to +50mA SMBCLK, SMBDATA, SMBSUS and ALERT to GND .............................................-0.3V to +6V ADD_ to GND ...............................................-0.3V to (V+ + 0.3V) SMBDATA and ALERT Sink Current ...................-1mA to +50mA Continuous Power Dissipation (TA = +70C) 16-Pin QSOP (derate 8.3mW/C above +70C)...........667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER Supply Voltage Range Static, outputs in any combination of on or off states up to 28V Supply Current (Note 2) Static, all IOs low or pulled to 0 SMBus interface operating, clock frequency = 100kHz POR Threshold Voltage I/O Sink Current I/O Current Limit I/O Leakage Current Propagation Delay Falling edge of V+ IO_ forced to 0.4V IO_ forced to 1.0V, V+ = 4.5V IO_, V+ = 4.5V IO_ forced to 28V SMBCLK to IO_ SMBSUS to IO_ IO_ to ALERT IO_ Data Set-Up Time IO_ Data Hold Time SMBus Logic Input Voltage Range Logic Input High Voltage Logic Input Low Voltage SMBus Output Low Sink Current ALERT Output Low Sink Current ALERT Output High Leakage Current Thermal Shutdown Sample Address Input Impedance Logic Input Current SMBus Input Capacitance 10% or 90% of I/O to 10% of SMBCLK (Note 3) (Note 3) SMBSUS, SMBCLK, SMBDATA (Note 2) IO_, SMBSUS, SMBCLK, SMBDATA IO_, SMBSUS, SMBCLK, SMBDATA SMBDATA forced to 0.6V ALERT forced to 0.4V ALERT forced to 5.5V 10C typical hysteresis ADD_ during address sampling (POR, SPOR, and RAP) to V+ and GND (Note 4) SMBDATA, SMBCLK, SMBUS, ADD_ SMBCLK, SMBDATA -1 5 140 20 1 6 1 1 10 3 0 2.1 0.8 5.5 1.2 2 8 15 13 25 0.5 50 2 2.5 1 10 s s V V V mA mA A C k A pF s CONDITIONS MIN 2.7 7 3.5 7 1.8 2.5 V mA mA A TYP MAX 5.5 18 9 A UNITS V
2
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Octal SMBus-to-Parallel I/O Expanders
TIMING CHARACTERISTICS
(V+ = +2.7V to +5.5V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1) PARAMETER SMBus Clock Frequency SMBCLK Clock Low Time SMBCLK Clock High Time SMBus Rise Time SMBus Fall Time SMBus Start-Condition Setup Time SMBus Repeated StartCondition Setup Time SMBus Start-Condition Hold Time SMBus Stop-Condition Setup Time SMBus Data Valid to SMBCLK Rising Edge Time SMBus Data Hold Time SMBCLK Falling Edge to SMBDATA Valid Time Note 1: Note 2: Note 3: Note 4: Note 5: tSU:STA tHD:STA tSU:STO tSU:DAT tHD:DAT Master clocking in data 90% to 90% points 10% of SMBDATA to 90% of SMBCLK 90% of SMBCLK to 10% of SMBDATA 10% or 90% of SMBDATA to 10% of SMBCLK tLOW tHIGH SYMBOL (Note 5) 10% to 10% points 90% to 90% points SMBCLK, SMBDATA; 10% to 90% points SMBCLK, SMBDATA; 90% to 10% points 4.7 500 4 4 250 300 3 CONDITIONS MIN DC 4.7 4 1 300 TYP MAX 100 UNITS kHz s s s ns s ns s s ns ns s
MAX1608/MAX1609
Specifications from 0C to -40C are guaranteed by design, not production tested. For supply current, SMBus logic inputs driven to 0 or V+. Data hold and set-up times measured from falling edge of 9th clock. Must be driven to GND, V+, or floating. See SMBus Addressing section. The SMBus logic block is a static design and will work with clock frequencies down to DC. While slow operation is possible, it violates the 10kHz minimum clock frequency and SMBus specifications and may use excessive space on the bus.
Typical Operating Characteristics
(V+ = +5V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1608/9 tTOC01
SUPPLY CURRENT vs. TEMPERATURE
MAX1608/9 TOC02
IO_ SINK CURRENT vs. SUPPLY VOLTAGE
14 VIO_ = 1.0V SINK CURRENT (mA) 12 10 8 6 4 VIO_ = 0.4V
MAX1608/9 TOC03
15.0 12.5 SUPPLY CURRENT (A) 10.0 7.5 IOs = 0000 0000 5.0 2.5 0 2.5 3.0 3.5 4.0 4.5 5.0 IOs = 1111 1111 PULLED UP TO +28V
15.0 12.5 SUPPLY CURRENT (A) 10.0 7.5 5.0 2.5 0 IOs = 1111 1111 PULLED UP TO +28V
16
IOs = 0000 0000
2 0 -40 -20 0 20 40 60 80 100 0 1 2 3 4 5 6 TEMPERATURE (C) SUPPLY VOLTAGE (V)
5.5
SUPPLY VOLTAGE (V)
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
Typical Operating Characteristics (continued)
(V+ = +5V, TA = +25C, unless otherwise noted.)
IO_ CURRENT LIMIT vs. TEMPERATURE
MAX1608/9 TOC04
IO_ CURRENT LIMIT vs. IO_ VOLTAGE
MAX1608/9 TOC05
IO_ CURRENT LIMIT vs. SUPPLY VOLTAGE
35 IO_ CURRENT LIMIT (mA) 30 25 20 15 10 5 0 2.5 3.0 3.5 4.0 4.5 VIO_ = 15V IO_ = 0 5.0 5.5
MAX1608/9 TOC06
40 IO_ = 0 PULLED UP TO +28V 35 IO_ CURRENT LIMIT (mA) 30 25 20 15 10 5 0 -40 -20 0 20 40 60 80
30 25 IO_ CURRENT LIMIT (mA) 20 15 10 5 0
40
V+ = 4.5V IO_ = 0 0 5 10 15 VIO_ (V) 20 25 30
100
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
IO_ BIAS CURRENT vs. IO_ VOLTAGE
MAX1608/9 TOC07
IO_ BIAS CURRENT vs. TEMPERATURE
MAX1608/9 TOC08
SUSPEND-STATE DELAY (IO_ RISING)
PULL-UP = 10k to 28V
MAX1608/9 TOC09
1.0 0.9 0.8 IO_ BIAS CURRENT (A) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 15 VIO_ (V) 20 25 IO_ = 1
1.0 V+ = 5V IO_ = 1 PULLED UP TO 28V 0.8 IO_ BIAS CURRENT (A)
0.6
IO_ 10V/div
0.4 SMBSUS 5V/div
0.2
30
0 -40 -20 0 20 40 60 80 100 TEMPERATURE (C) 100ns/div
SUSPEND-STATE DELAY (IO_ FALLING)
MAX1608/9 TOC010
ALERT DELAY (IO_ RISING)
MAX1608/9 TOC011
PULL-UP = 10k to 28V
IO_ 10V/div
IO_ 2V/div
SMBSUS 5V/div IO_ DRIVEN EXTERNALLY 100ns/div 40ns/div
ALERT 5V/div
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Octal SMBus-to-Parallel I/O Expanders
Typical Operating Characteristics (continued)
(V+ = +5V, TA = +25C, unless otherwise noted.)
MAX1608/MAX1609
ALERT DELAY (IO_ FALLING)
MAX1608/9 TOC012
MAX1608 IO_ POWER-UP RESPONSE
PULL-UP = 10k to V+
MAX1608/9 TOC013
IO_ 2V/div
VIO_ 500mV/div
ALERT 5V/div IO_ DRIVEN EXTERNALLY 200ns/div
V+ 2V/div
Pin Description
PIN 1- 8 9 10, 11 12 13 14 15 16 NAME IO0- IO7 GND ADD0, ADD1 SMBDATA ALERT SMBCLK SMBSUS V+ FUNCTION Combined Input/Output. Open-drain output. Can withstand +28V. Ground SMBus Address Select. See Table 1. SMBus Serial-Data Input/Output. Open-drain output. Requires external pull-up resistor. Active-Low Interrupt Output. Open-drain output. Requires external pull-up resistor. SMBus Serial Clock Input SMBus Suspend-Mode Control Input. The device will enter the state previously stored in the suspend-mode registers if low, or enter the state previously stored in the normal-mode registers if high. Supply Voltage Input, +2.7V to +5.5V. Bypass to GND with a 0.1F capacitor.
Detailed Description
The MAX1608/MAX1609 convert 2-wire SMBus serial data into eight latched parallel outputs (IO0-IO7). These devices are intended for general-purpose remote I/O expansion. Each device has eight high-voltage opendrain outputs that double as TTL-level logic inputs. Typical applications range from high-side MOSFET loadswitch drivers in power-management systems, to pushbutton switch monitors, to general-purpose digital I/Os. The MAX1608/MAX1609 include two complete sets of registers, each consisting of one output data register to
set the output states and two interrupt mask registers. The SMBSUS line selects which set of registers control the device state. The input register is used to perform readback of the actual IO states. The MAX1608/MAX1609 operate from a single +2.7V to +5.5V supply with a typical quiescent current of 2.5A, making them ideal for portable applications. Additionally, the devices include an ALERT function to alert the master of change of condition (Figure 1).
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
SMBCLK SMBDATA SMB
8
COMMAND DECODER IO1 INPUT REGISTER 8 IO2
8 NORMAL RISING INTERRUPT MASK REGISTER 8 IO7 8 ADD0 ADD1 ADDRESS DECODER SUSPEND RISING INTERRUPT MASK REGISTER TRANSITION DETECTORS 1
7 NORMAL FALLING INTERRUPT MASK REGISTER 1 SUSPEND FALLING INTERRUPT MASK REGISTER ALERT R FAULT LATCH S NORMAL OUTPUT REGISTER THERMAL SHUTDOWN 8
ALERT RESPONSE REGISTER
1 SUSPEND OUTPUT REGISTER 8
SMBSUS
Figure 1. Functional Diagram
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Octal SMBus-to-Parallel I/O Expanders
SMBus Interface Operation
The SMBus serial interface is a 2-wire interface with multi-mastering capability. The MAX1608/MAX1609 are 2-wire slave-only devices and employ standard SMBus write-byte, send-byte, read-byte, and receive-byte protocols (Figure 2) as documented in "System Management Bus Specification v1.08" (available at www.sbs-forum.org). SMBDATA and SMBCLK are Schmitt-triggered inputs that can accommodate slower edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. Communication starts with the master signaling the beginning of a transmission with a START condition, which is a high-to-low transition on SMBDATA while SMBCLK is high. When the master has finished communicating with the slave, it issues a STOP condition, which is a low-to-high transition on SMBDATA while SMBCLK is high (Figures 3 and 4). The bus is then free for another transmission from any master on the bus. The address byte, command byte, and data byte are transmitted between the START and STOP conditions. Figures 3 and 4 show the timing diagrams for signals on the 2-wire interface. The SMBDATA state is allowed to change only while SMBCLK is low, except for the START and STOP conditions. Data is transmitted in 8bit words and is sampled on the rising edge of SMBCLK. Nine clock cycles are required to transfer each byte in or out of the MAX1608/MAX1609 (Figure 2), since either the master or the slave acknowledges receipt of the correct byte during the ninth clock. The IC responds to the address selected by the ADD0 and ADD1 pins (Table 1). If the MAX1608/MAX1609 receive the correct slave address followed by RW = 0, the selected device expects to receive one or two bytes of information. If the device detects a START or STOP condition prior to clocking in a full additional byte of data, it considers this an error condition and disregards all of the data. If no error occurs, the registers are updated immediately after the falling edge of the acknowledge clock pulse (Figure 5). If the MAX1608/MAX1609 receive the correct slave address followed by RW = 1, the selected device expects to clock out the contents of the previously accessed register during the next byte transfer. A third interface line (SMBSUS) is used to execute commands asynchronously from previously stored registers (see SMBSUS (Suspend-Mode) Input section).
MAX1608/MAX1609
Table 1. Slave Addresses
ADDRESS (A6-A0) ADD0 GND GND GND High-Z High-Z High-Z V+ V+ V+ ADD1 MAX1608 GND High-Z V+ GND High-Z V+ GND High-Z V+ 0010 100 0010 101 0010 110 1100 100 1100 101 1100 110 0111 000 0111 001 0111 010 MAX1609 0100 100 0100 101 0100 110 1101 100 1101 101 1101 110 0110 000 0110 001 0110 010
MAX1608/MAX1609 recognizes its own address, it sends an acknowledgment pulse by pulling SMBDATA low. Each slave responds to only two addresses: its own unique address (set by ADD1 and ADD0, Table 1), and the alert response address (0x19). The device's unique address is determined at power-up, with a software sample-address-pin command (SAP), or a software power-on-reset command (SPOR). The MAX1608/ MAX1609 address pins (ADD1-ADD0) are high impedance except when ADD1-ADD0 are sampled, which occurs during power-up and when requested (SPOR, RAP). During sampling, the equivalent input circuit can be described as a resistor-divider from V+ to GND (20k each), which momentarily bias the pins to midsupply if they are left floating. To set the ADD_ pins high or low, connect or drive the pins to the rails (V+ or GND) to guarantee a correct level detection. During sampling, the pins draw a momentary input bias current (V+ / 20k). Also, stray capacitance in excess of 50pF on the ADD_ pins when floating may cause address recognition problems.
SMBus Commands
The 8-bit command byte (Table 2) is the master index that points to the registers within the MAX1608/MAX1609. The devices include ten registers: the data registers (NDR1-NDR3, SDR1-SDR3) are accessed through both the read-byte and write-byte protocols (Figure 2), the RSB and MDIF registers are accessed with the read-byte protocols, and the RAP and SPOR registers
SMBus Addressing
After the START condition, the master transmits a 7-bit address followed by the RW bit (Figure 2). If the
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
use the send-byte protocol. The shorter receive-byte protocol can be used instead of the read-byte protocol, provided the correct data register was previously selected by a read-byte or write-byte instruction. Use caution with the shorter protocols in multimaster systems, since a second master could overwrite the command byte without informing the first master. The register selected at POR is 0b0000 0000 so that a receive-byte transmission that occurs immediately after initial power-up returns the setting of NDR1. SPOR does not reset the register pointer. When using an external pull-up, high impedance corresponds to an output high. To use the IO_ pins as TTL inputs only, set the corresponding bit high. The MAX1608 powers up with all IO_ pins set low; the MAX1609 powers up with all IO_ pins set to high impedance (Table 3). Register 2 (NDR2 and SDR2) are used to mask risingedge triggered interrupts, while Register 3 are used to mask falling-edge triggered interrupts. On power-up, all interrupts are masked (Tables 4 and 5). The IO_ Status Data Register (RSB, Table 6) reads the actual TTL-logic level of the IO_ pins. The IO_ pins are sampled on the falling edge of the third byte's acknowledge (ACK) for a read-byte format, or on the falling edge of the first byte's ACK for a receive-byte protocol (Figure 5). There is a 15s data-setup time requirement, due to the slow level translators needed for highvoltage (28V) operation. Data-hold time is 300ns. Do not write to the RSB register because writes to readonly registers are redirected to NDR1. SMBus sends
Data Registers
The MAX1608/MAX1609 each have seven data registers, three normal registers, three suspend registers, and one readback register. The SMBUS line determines which registers controls the output states and the interrupt mask states (normal registers if SUSBUS = 1, suspend registers if SMBSUS = 0). Registers 1 (NDR1 and SDR1) set the state of each of the eight outputs to either low or high impedance.
Write-Byte Format S ADDRESS 7 bits Slave Address WR 1b ACK 1b COMMAND 8 bits Command Byte: selects which register you are writing to ACK 1b DATA 8 bits ACK 1b P
Data Byte: data goes into the register set by the command byte
Read-Byte Format S ADDRESS 7 bits Slave Address WR 1b ACK 1b COMMAND 8 bits ACK 1b S ADDRESS 7 bits RD 1b ACK 1b DATA 8 bits /// 1b P
Command Byte: selects which register you are reading from
Slave Address: repeated due to change in dataflow direction
Data Byte: reads from the register set by the command byte
Send-Byte Format S ADDRESS 7 bits WR 1b ACK 1b COMMAND 8 bits ACK 1b P
Receive-Byte Format S ADDRESS 7 bits RD 1b ACK 1b DATA 8 bits /// 1b P
Command Byte: sends command with no data; usually used for oneshot command S = Start condition P = Stop condition Shaded = Slave transmission Ack= Acknowledged = 0 /// = Not acknowledged = 1 WR = Write = 0 RD = Read =1
Slave Address
Data Byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for SMBus Alert Response return address
Figure 2. SMBus Protocols 8 _______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
A
tLOW
B
tHIGH
C
D
E
F
G
H
I
J
K
L
M
SMBCLK
SMBDATA
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tHD:DAT
tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION
A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW
Figure 3. SMBus Write Timing
A tLOW
B tHIGH
C
D
E
F
G
H
I
J
K
SMBCLK
SMBDATA
tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE
tSU:DAT
tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER
tSU:DAT
tSU:STO
tBUF
I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION
Figure 4. SMBus Read Timing
data MSB first; therefore, IO7, MASK7, and data 7 bit correspond to the MSB (first bit of the data byte).
Other Registers
RAP uses the send-byte protocol to resample the address pins. Do not use read- and write-byte protocols to RAP because data is redirected to NDR1 although the ADD_ pins will be sampled. SPOR uses the send-byte protocol to resample the address pins and reset the registers to the POR state. Do not use read- and write-byte protocols to SPOR because data is redirected to NDR1 although the function will be performed.
MFID uses the read-byte protocol to access the ID register. Do not use write-byte protocol to MFID because data is redirected to NDR1.
SMBSUS (Suspend-Mode) Input
The state of the SMBSUS input selects which register contents (NDR1 or SDR1) are applied to the IO_ pins and which set of registers are used to mask the interrupts (NDR2, NDR3 or NDR2, SDR3). Driving SMBSUS low selects the suspend-mode registers, while driving SMBSUS high selects the normal registers. This feature allows the system to select between two different I/O
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
configurations asynchronously, eliminating latencies introduced by the serial bus.
LAST BIT CLOCKED INTO SLAVE** ACKNOWLEDGE BIT CLOCKED INTO MASTER
ALERT
The MAX1608/MAX1609 can generate hardware interrupts whenever the logic states of the IO_ pins change or when thermal shutdown occurs. Interrupts are signaled on the ALERT pin. The IO_ interrupts can be masked individually through the mask registers. Registers NDR2 and SDR2 mask the IO_ rising-edge interrupts, while NDR3 and SDR3 mask the IO_ fallingedge interrupts. The power-on-reset state masks all interrupts (Tables 4 and 5).
tDH:DAT STOP
SCL
SDA tDH:DAT
SLAVE PULLING SDA LOW
REGISTERS UPDATED* IO_TRANSITION
The thermal-shutdown protection also generates an interrupt. This interrupt cannot be masked (see Thermal Shutdown section). An interrupt can be cleared with a SPOR or an Alert Response. However, after an interrupt has occurred, masking will not clear it. Alert Response Address (0b00011001) The alert response (interrupt pointer) address provides quick fault identification for simple slave devices that cannot initiate communication as a bus master. When a slave device generates an interrupt, the host (bus master) interrogates the bus slave devices through a special receive-byte operation that includes the alert response address (0x19). The offending slave device returns its own address during this receive-byte operation. The interrupt pointer address can activate several different slave devices simultaneously. If more than one
IO_ tSCL:IO *NDR#, SDR# ARE LOADED. RAP, SPOR ARE INITIATED. RSB IS SAMPLED. **DURING A RECEIVE-BYTE PROTOCOL, CORRESPONDS TO THE R/W BIT. DURING A READ/WRITE-BYTE PROTOCOL, CORRESPONDS TO LAST BIT OF DATA.
Figure 5. Registers/IO_ Update Timing Diagram
Table 2. Command-Byte/Register Assignment
POR STATE REGISTER NDR1 NDR2 NDR3 SDR1 SDR2 SDR3 RSB RAP SPOR MFID 10 COMMAND MAX1608 00h 01h 02h 03h 04h 05h 06h 07h 08h FEh 0000 0000 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 -- -- -- 4Dh MAX1609 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 -- -- -- 4Dh Normal Data Register 1. Sets the IO_ states. Normal Data Register 2. Masks the L/H interrupt. Normal Data Register 3. Masks the H/L interrupt. Suspend Data Register 1. Sets the IO_ states. Suspend Data Register 2. Masks the L/H interrupt. Suspend Data Register 3. Masks the H/L interrupt. IO_ Status Data Register. Read pin state. Sample the address pins. Execute software POR and samples address pins. Read manufacturer ID (ASCII code for "M"axim). FUNCTION
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
Table 3. Data Register 1 (NDR1 and SDR1) Bit Assignments (read or write)
POR STATE BIT 7 6 5 4 3 2 1 0 NAME MAX1608 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 0 0 0 0 0 0 0 0 MAX1609 1 1 1 1 1 1 1 1 Sets IO7 state. 0 = on (low state), 1 = off (high-impedance). Sets IO6 state. 0 = on (low state), 1 = off (high-impedance). Sets IO5 state. 0 = on (low state), 1 = off (high-impedance). Sets IO4 state. 0 = on (low state), 1 = off (high-impedance). Sets IO3 state. 0 = on (low state), 1 = off (high-impedance). Sets IO2 state. 0 = on (low state), 1 = off (high-impedance). Sets IO1 state. 0 = on (low state), 1 = off (high-impedance). Sets IO0 state. 0 = on (low state), 1 = off (high-impedance). FUNCTION
Table 4. Data Register 2 (NDR2 and SDR2) Bit Assignments (read or write)
BIT 7 6 5 4 3 2 1 0 NAME MASKH7 MASKH6 MASKH5 MASKH4 MASKH3 MASKH2 MASKH1 MASKH0 POR STATE 1 1 1 1 1 1 1 1 FUNCTION Masks IO7 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO6 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO5 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO4 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO3 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO2 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO1 low-to-high interrupt. 0 = interrupts, 1 = masked. Masks IO0 low-to-high interrupt. 0 = interrupts, 1 = masked.
slave attempts to respond, bus arbitration rules apply, with the lowest address code going first. The other device(s) will not generate an acknowledge and will continue to hold the ALERT pin low until it is allowed to clear its own interrupt. Clearing the interrupt has no effect on the state of the status registers.
External pull-up resistors and IO_ sink capability can affect the outputs' rise and fall times. When using the MAX1608/MAX1609 to control an external MOSFET in power-switching applications, pull-up and/or series resistance can be used together with the MOSFET's gate capacitance or additional external capacitance (Figure 6) to control the transition time of the switched source. The input logic levels are TTL compatible and are sampled during a readback SMBus transmission (see RSB register in Data Registers section ).
Input/Output Pins
Each IO_ pin is protected by an internal 20mA (typical) current-limit circuit. Typical pull-down on-resistance at VCC = +2.7V and +5.5V is 100 and 66, respectively. When the IO_ is high impedance, it actually has a 0.5A pull-down current source included as part of the read-back functionality.
Power-On Reset
The MAX1608/MAX1609's power-on-reset circuit ensures that the IO_ states are defined when V+ is first applied or when the supply dips below the UVLO
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Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
Table 5. IO_ Status Data Register (RSB) Bit Assignments (read only)
BIT 7 6 5 4 3 2 1 0 NAME MASKL7 MASKL6 MASKL5 MASKL4 MASKL3 MASKL2 MASKL1 MASKL0 POR STATE 1 1 1 1 1 1 1 1 FUNCTION Masks IO7 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO6 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO5 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO4 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO3 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO2 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO1 high-to-low interrupt. 0 = interrupts, 1 = masked. Masks IO0 high-to-low interrupt. 0 = interrupts, 1 = masked.
Table 6. Data Register 3 (NDR3 and SDR3) Bit Assignments (read or write)
BIT 7 6 5 4 3 2 1 0 NAME DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 FUNCTION Indicates the current state of IO7. 1 = high, 0 = low. Indicates the current state of IO6. 1 = high, 0 = low. Indicates the current state of IO5. 1 = high, 0 = low. Indicates the current state of IO4. 1 = high, 0 = low. Indicates the current state of IO3. 1 = high, 0 = low. Indicates the current state of IO2. 1 = high, 0 = low. Indicates the current state of IO1. 1 = high, 0 = low. Indicates the current state of IO0. 1 = high, 0 = low.
threshold. The power-on states can also be reset with the SPOR command through the SMBus. The MAX1608's outputs reset to a low state, while the MAX1609's outputs reset to a high-impedance state. Below V+ = 0.8V (typical), the POR states can't be enforced, and the I/O pins of both devices exhibit increasingly weak pull-down current capability, eventually becoming high impedance. The MAX1608 is designed for applications that control N-channel MOSFETs, while the MAX1609 is designed to control P-channel MOSFETs. The power-on state keeps the external MOSFETs off at power-up. Both devices are suited for applications that use the parallel input for serial functionality, although IO_s serving as inputs must first be programmed to high impedance when using the MAX1608.
Thermal Shutdown
These devices have internal thermal-shutdown circuitry that sets all outputs to a high-impedance state (IO_ pins) when the junction temperature exceeds +140C typical. Thermal shutdown only occurs during an overload condition on the IO_ pins. The device cycles between thermal shutdown and the overcurrent condition (with 10C hysteresis) until the overload condition is removed. The device asserts ALERT low while it is in thermal shutdown, indicating this fault status. ALERT will be reasserted immediately after it is cleared if the device is still hot. ALERT can only be completely cleared once the fault condition is removed and the device has cooled. Alternatively, forcing the IO_ to high impedance will allow the junction to cool down.
12
______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
+5V
10k
10k
10k
V+
10k 0.1F 200k
0.01F*
10k
0.01F*
10k
0.01F*
MAX1609
ALERT TO/FROM HOST SMBDATA SMBCLK SMBSUS ADD0 ADD1 GND IO7 IO0 IO1 IO2
200k IRF7406 IRF7406
200k IRF7406
LOAD1
LOAD2
LOAD3
+12V +5V
10k
10k
10k 0.1F
V+
10k
10k IRF7413
10k IRF7413 200k 200k 0.01F* 0.01F* IRF7413
MAX1608
ALERT IO0 IO1 IO2
200k 0.01F*
TO/FROM HOST
SMBDATA SMBCLK SMBSUS ADD0
LOAD1 ADD1 GND IO7
LOAD2
LOAD3 *OPTIONAL
Figure 6. Load Switch with Controlled Turn-On
Application Examples
P-Channel/N-Channel High-Side Load Switch with Controlled Turn-On
In load-switching applications, when a controlled voltage ramp or inrush current limiting is required, add a series resistor to slow the switch turn-on and turn-off times. The external MOSFET gate has a typical capacitance of 150pF to 2000pF, but an optional external capacitance can be added to further slow the switching time (Figure 6). If a slow turn-on time is required, simply use an N-channel MOSFET with a high-value pull-up resistor and no series resistor. Similarly, if a fast turn-on and a slow turn-off are desired, use a P-channel MOSFET with a high-value pull-up resistor and no series resistor.
Battery Switch with Back-to-Back MOSFETs
Many battery-operated applications use back-to-back MOSFETs to prevent reverse currents from the load to the supply (Figure 7). This protects the battery from potential damage and isolates the load from the power source.
LED Driver
A MAX1608/MAX1609 can be used as programmable LED drivers (Figure 8). With their low quiescent current, these devices are ideal for use as indicator light drivers on the front panel of a notebook computer.
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13
Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
+5V +3.3V TO +28V
100k 10k 10k 10k V+ 0.1F IRF7406 P
MAX1609
75k* ALERT TO/FROM HOST SMBDATA IRF7406 SMBCLK SMBSUS ADD0 ADD1 GND NOTE: OTHER OUTPUTS CAN BE CONFIGURED SIMILARLY. *75k RESISTOR FOR VOLTAGES GREATER THAN +12V. IO7 LOAD P IO0 1M
Figure 7. Battery Switch with Back-to-Back MOSFETs
+5V
1k 10k 10k V+ 0.1F
1k
1k
MAX1608 MAX1609
ALERT SMBDATA TO/FROM HOST SMBCLK SMBSUS ADD0 ADD1 GND IO7 IO0 IO1 IO2
Figure 8. LED Driver
Mechanical Switch Monitor
The MAX1608/MAX1609's ability to perform IO_ logicstate readback makes them suitable for checking system status. They can be used as an "open-lid indicator," sensing a change in the IO_ and sending an interrupt to the master to indicate a change in status (Figure 9). The same can be done to detect a chassis intrusion, a reset switch, or a card insertion.
Simple High-Voltage Switch
For applications requiring a higher voltage, use a simple resistive divider to protect the gate from breakdown yet allow the MOSFETs to handle higher voltage applications (Figure 10).
___________________Chip Information
TRANSISTOR COUNT: 5762
14
______________________________________________________________________________________
Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
+5V 0.1F
10k
10k
10k
V+
100k
100k
100k
MAX1608 MAX1609
ALERT TO/FROM HOST SMBDATA SMBCLK SMBSUS ADD0 ADD1 GND IO7 I/O0 I/O1 I/O2
Figure 9. Mechanical Switch Monitor
+5V
VIN = 10V TO 28V
200k 10k 10k 10k VCC 0.1F 0.01F* 200k ALERT TO/FROM HOST SMBCLK SMBDATA SMBSUS ADD0 ADD1 GND IO7 IO1 IO2 IO3 IO4 LOAD IRF7406
MAX1609
Figure 10. Simple High-Voltage Switch
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15
Octal SMBus-to-Parallel I/O Expanders MAX1608/MAX1609
Typical Operating Circuits (continued)
+2.7V TO +5.5V V+ 100k 0.1F 100k 100k +12V
MAX1608
ALERT SMBUS TO/ FROM HOST I00 SMBDATA I01 SMBCLK I02 SMBSUS ADD0 LOAD1 ADD1 GND I07 LOAD2 LOAD3 N-CH
Package Information
QSOP.EPS
Note: MAX1608/MAX1609 do not have a heat slug.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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